Olek's blog

To content | To menu | To search

Tag - FPGA

Entries feed

Friday, August 14 2015

How to generate MCS file from Vivado?

There is still one function missing from Vivado 2015.2 - namely, the UI-accessible MCS file generation for FLASH memories. For now you can enter the "write_cfgmem" command in the TCL shell and play with its arguments. This is however not very user friendly.

Fortunately, the process can be easily automated by yourself! You can use "Tools" => "Customize commands" => "Customize Commands..." to add own buttons triggering TCL scripts. Knowning the "write_cfgmem" command, the only problem is how to get the path to the currently used bit file? I propose to do the complete solution like this:

write_cfgmem -force -format MCS -size 128 -interface SPIx4 -loadbit "up 0x0 [glob [get_property DIRECTORY [current_project]]/[get_property NAME [current_project]].runs/impl_1/*.bit]" "[get_property DIRECTORY [current_project]]/spi_mem.mcs"

This method should work until someone have several implementation runs in one project. This particular command generates MCS FLASH file called "spi_mem" for 128 M QSPI memory.

Saturday, December 22 2012

Problems with Xilinx I2C MicroBlaze module

When using long cables with Xilinx I2C peripherals (xps_iic or axi_iic) the bus controller may behave unexpectedly. Sometimes it just hangs during send operation, and sometimes it starts generating SCL clock signal forever. The issue seems to be related to the signal reflection from the remote end of the cable. In the particular case it was solved by mounting 22 pF capacitors to ground on both I2C lines, close to the FPGA circuit.